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- 24-core 512GB
- 32-core 64GB
- 32-core 256GB
- 32-core 512GB
- 40-core 96GB
- 40-core 192GB
- 56-core 128GB
- 56-core 256GB
- 56-core 512GB
- 64-core 192GB
- 64-core 384GB
- 64-core 768GB
- 80-core 96GB
- 80-core 192GB
- 80-core 384GB
- 80-core 768GB
- 80-core 1.5TB
The Argon cluster is split between two data centers,
- ITF → Information Technology Facility
- LC→ Lindquist Center
Most of the nodes in the LC datacenter are connected with the OmniPath high speed interconnect fabric, while most of those in the ITF data center are connected with the InfiniPath fabric, with the latest nodes having a Mellanox Infiniband EDR fabric. There are imany machines with varying types of GPU accelerators:
- 21 machines with Nvidia P100 accelerators
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- 2 machines with Nvidia K80 accelerators
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- 11 machines with NVidia K20 accelerators
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- 2 machines with Nvidia P40 accelerators
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- 17 machines with 1080Ti accelerators
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- 19 machines with Titan V accelerators
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- 4 machines with V100 accelerators
- 28 machines with 2080Ti accelerators
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The Titan V is now considered as a supported configuration in Argon phase 1 GPU-capable compute nodes but is restricted to a single card per node. Staff have completed the qualification process for the 1080 Ti and concluded that it is not a viable solution to add to phase 1 Argon compute nodes. |
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The Rpeak needs to be updated. |
The Rpeak (theoretical Flops) is 385.0 TFlops, not including the accelerators, with 112 TB of memory. In addition, there are 2 login nodes of the Broadwell system architecture, with 256GB of memory each.
While on the backend Argon was completely new architecture in Feb. 2017, the frontend should be very familiar to those who have used previous generation HPC systems at the University of Iowa. There are, however, a few key differences that will be discussed in this page.
Heterogeneity
While previous HPC cluster systems at UI have been very homogenous, the Argon HPC system has a heterogeneous mix of compute node types. In addition to the variability in the GPU accelerator types listed above, there are also differences in CPU architecture. We generally follow Intel marketing names, with the most important distinction being the AVX (Advanced Vector Extensions) unit on the processor. The following table lists the processors in increasing generational order.
| Architecture | AVX level | Floating Point Operations per cycle |
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| Sandybridge Ivybridge | AVX | 8 |
| Haswell Broadwell | AVX2 | 16 |
| Skylake Silver | AVX512 | 16 (1) AVX unit per processor core |
| Skylake Gold | AVX512 | 32 (2) AVX units per processor core |
| Cascade Lake Gold | AVX512 | 32 |
Note that code must be optimized during compilation to take advantage of AVX instructions. The CPU architecture is important to keep in mind both in terms of potential performance and compatibility. For instance, code optimized for AVX2 instructions will not run on the Sandybridge/Ivybridge architecture because it only supports AVX, not AVX2. However, each successive generation is backward compatible so code optimized with AVX instructions will run on Haswell/Broadwell systems.
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Using the Basic Job Submission and Advanced Job Submission pages as a reference, how would one submit jobs taking HT into account? For single process high throughput type jobs it probably does not matter, just request one slot per job. For multithreaded or MPI jobs, request one job slot per thread or process. So if your application runs best with 4 threads then request something like the following.
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