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The University of Iowa's Argon HPC system was deployed in February, 2017. There are several compute node configurations,
- 24-core 512GB
- 32-core 64GB
- 32-core 256GB
- 32-core 512GB
- 40-core 96GB
- 40-core 192GB
- 56-core 128GB
- 56-core 256GB
- 56-core 512GB
- 64-core 192GB
- 64-core 384GB
- 64-core 768GB
- 80-core 96GB
- 80-core 192GB
- 80-core 384GB
- 80-core 768GB
- 80-core 1.5TB
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- 21 machines with Nvidia P100 accelerators
- 2 machines with Nvidia K80 accelerators11 machines with NVidia K20 accelerators
- 2 machines with Nvidia P40 accelerators
- 17 machines with 1080Ti accelerators
- 19 machines with Titan V accelerators
- 14 machines with V100 accelerators
- 38 machines with 2080Ti accelerators
- 1 machine with RTX8000 accelerators
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Architecture | AVX level | Floating Point Operations per cycle | Sandybridge Ivybridge | AVX | 8|
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Haswell Broadwell | AVX2 | 16 | |||
Skylake Silver | AVX512 | 16 (1) AVX unit per processor core | |||
Skylake Gold | AVX512 | 32 (2) AVX units per processor core | |||
Cascade Lake Cascadelake Gold | AVX512 | 32 |
Note that code must be optimized during compilation to take advantage of AVX instructions. The CPU architecture is important to keep in mind both in terms of potential performance and compatibility. For instance, code optimized for AVX2 AVX512 instructions will not run on the SandybridgeHaswell/Ivybridge Broadwell architecture because it only supports AVXAVX2, not AVX2AVX512. However, each successive generation is backward compatible so code optimized with AVX AVX2 instructions will run on HaswellSkylake/Broadwell Cascadelake systems.
Hyper Threaded Cores (HT)
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